1. Field of the Invention
The present invention relates in general to an erasable programmable read-only memory (EPROM) and method of forming the same. In particular, the present invention relates to a method of fabricating a single-poly EPROM compatible with complementary metal oxide semiconductor (CMOS) process and structure of the same.
2. Description of the Related Art
A single-poly erasable programmable read-only memory (EPROM) cell is a non-volatile storage device fabricated using process steps fully compatible with conventional single-poly CMOS fabrication process steps. As a result, single-poly EPROM cells are often embedded in CMOS logic and mixed-signal circuits.
FIGS. 1A-1C show a series of views that illustrate a conventional single-poly EPROM cell 10. FIG. 1A shows a plan view of cell 10, FIG. 1B shows a cross-section taken along line 1Bxe2x80x941B of FIG. 1A, while FIG. 1C shows a cross-section taken along line 1Cxe2x80x941C of FIG. 1A.
As shown in FIGS. 1A-1C, EPROM cell 10 includes spaced-apart source and drain regions 14 and 16, respectively, formed in a p-type semiconductor material 12, such as a well or a substrate, and a channel region 118 defined between source and drain regions 14 and 16.
As further shown in FIGS. 1A-1C, cell 10 also includes an n-well 20 formed in p-type material 12, and a field oxide region FOX formed in p-type material 12 to isolate source region 14, drain region 16, and channel region 18 from n-well 20.
In addition, cell 10 further includes adjoining p+ and n+ contact regions 22 and 24, respectively, formed in n-well 20. Current generation cells also include a p-type lightly doped drain (PLDD) region 26, which adjoins p+ contact region 22.
Further, a control gate region 28 is defined between PLDD region 26 and the field oxide region FOX that isolates n-well 20 from source region 14, drain region 16, and channel region 18. In addition, a layer of gate oxide 30 is formed over channel region 18, a layer of control gate oxide 32 is formed over control gate region 28, and a floating gate 34 is formed over gate oxide layer 30, control gate oxide layer 32, and a portion of the field oxide region FOX.
However, a cell cannot be shrunk in this type of single-poly EPROM, thus its density cannot be enhanced.
It is an object of the present invention to provide a single-poly EPROM with higher cell density and a method for forming the same.
It is another object of the present invention to provide a single-poly EPROM in which a single-poly EPROM cell is programmed with source side injection, improving its programming efficiency.
According to one aspect of the present invention, a pair of single-poly EPROM cell in a substrate is provided. The structure comprises an isolation region disposed in the substrate to define a striped active area. A deep well of first conductive type is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at the striped active area. A pair of selective gates are disposed on the gate oxide layer and the isolation region, and the pair of selective gates are striped-sharp and perpendicular to the striped active area. A pair of floating gates are disposed on the gate oxide layer corresponding to the active area, with a gap between the pair of floating gates and the pair of selective gates. A well of second conductive type is disposed in the deep well of first conductive type between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources are disposed on both sides of the well of second conductive type, and the pair of sources are connected to each other through the deep well of first conductive type. A drain is disposed in the well of second conductive type between the pair of selective gates.
A method for programming a memory cell of a single-poly EPROM is provided. For the above-mentioned structure of a pair of memory cells sharing a drain, the programming method comprises the step of applying programming bias voltages to a selected memory cell as follows. A first positive voltage of about 1.5-2 V is applied to the selective gate of the selected memory cell. A second positive voltage of about 10-12 V is applied to the pair of sources. The well of second conductive type, the drain, and the selective gate of the other unselected memory cell are all grounded. Thus, the programming bias voltages cause charge carriers source side injection (SSI) to accumulate in the floating gate of the selected memory cell.
A method for reading memory cell of a single-poly EPROM is provided. For the above-mentioned structure of a pair of memory cells sharing a drain, the reading method comprises the step of applying reading bias voltages to a selected memory cell as follows. A first positive voltage of Vcc is applied to the selective gate of the selected memory cell. A second positive voltage of about 2 V is applied to the drain. The selective gate of the other unselected,memory cell is grounded.
According to another aspect of the present invention, a method of fabricating a pair of single-poly EPROM cells, compatible with CMOS process is provided. A substrate having an isolation region therein to define a striped active area is provided. A deep well of first conductive type is formed under the isolation region and the striped active area. A gate oxide layer is formed on the striped active area. A conductive layer is formed on the gate oxide layer. The conductive layer is defined to form a pair of floating gates and a pair of selective gates, and a gap exists between the pair of floating gates and the pair of selective gates. The pair of selective gates are striped and perpendicular to the striped active area, and the pair of floating gates are islanded-shape. A well of second conductive type is formed in the deep well of first conductive type between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources is formed, and the pair of sources are connected to each other through the deep well of first conductive type. A drain is formed in the well of second conductive type between the pair of selective gates.
According to an embodiment of the present invention, the method of forming the pair of floating gates and the pair of selective gates comprises: forming a mask layer on the conductive layer, the mask layer substantially having a pattern of the pair of floating gates and the pair of selective gates; forming a plurality of spacers on the side walls of the mask layer, wherein the width of the gap between the pair of floating gates and the pair of selective gates is controlled by the spacers; and etching the conductive layer using the mask layer the spacers as an etching mask.